The 93k platform is designed around a scalable architecture that allows for "per-pin" resources. Unlike traditional testers that share resources across multiple pins, the 93k provides dedicated timing, levels, and pattern memory for each channel. This ensures that complex System-on-Chip (SoC) devices can be tested with maximum precision.
When the tester behaves unexpectedly, the manual suggests a "divide and conquer" approach. First, verify the hardware by swapping a suspected bad PE card with a known good one. Second, use the tool in SmarTest to inspect real-time waveforms. This allows you to see exactly where a timing edge is falling relative to the data window. verigy 93k tester manual
Measuring setup/hold times and propagation delays. Advanced Troubleshooting Tips The 93k platform is designed around a scalable
This section explains how to map logical device pins to physical tester channels. It covers the setup of different pin types, such as High-Speed Digital, Analog, or Power Supply pins. When the tester behaves unexpectedly, the manual suggests
To ensure repeatable results across different testers, the Verigy 93k manual emphasizes strict calibration routines.
The 93k uses an equation-based timing system. Instead of hard-coding values, engineers use variables to define cycle times and edge placements, allowing for easy frequency scaling during characterization.
💡 Always maintain a "Golden Device." If a test fails across multiple units, run the Golden Device to determine if the issue lies with the tester hardware or the test program itself.