: Moving registers across combinational logic boundaries to balance path delays without changing the design’s functionality.
: Paths that cannot be sensitized or don't need to meet timing (e.g., asynchronous reset synchronizers). synopsys timing constraints and optimization user guide 2021
: Optimizing logic across hierarchical boundaries to remove redundant gates and improve timing. : Moving registers across combinational logic boundaries to
The 2021 guide emphasizes PrimeTime as the industry "golden" signoff tool. synopsys timing constraints and optimization user guide 2021
The 2021 documentation introduced enhanced support for advanced process nodes (7nm and below) where parasitic effects are dominant.